1. Field of the Invention
The present invention relates to an error control apparatus, and in particular to an error control apparatus on a receiving side using a Hybrid Automatic Repeat reQuest (hereinafter, occasionally abbreviated as HARQ) which combines a Forward Error Correction (FEC) method and an ARQ method.
Recently, together with a rapid development of a communication technology, a data communication has been used in all of the fields, which has made reliability of the data communication more and more important.
2. Description of the Related Art
As an error control method of a data communication, there are following methods: (1) an error correcting method by which communication data are encoded into an error correcting code on a transmitting side (end), and the error correcting code is decoded on a receiving side (end) to obtain the communication data; and (2) an ARQ method by which communication data are encoded into an error detecting code on the transmitting side and an error is detected based on the error detecting code on the receiving side to perform a repeat request of the communication data when the error is detected.
Generally, the error correcting method (1) is used in many cases to reduce a Bit Error Rate (BER) in a communication for which real time performance is required for in a voice communication. On the other hand, the ARQ method (2) is used for the data communication in which high reliability is required for in a file transfer but a delay is permitted to some extent.
Also, for performing a more efficient error control, a HARQ combining the error correcting method (1) and the ARQ method (2) is used.
In a 3GPP (third Generation Partnership Project) in which W-CDMA that is one of the third generation mobile communication methods is standardized, the use of the HARQ as an error control technology of an HSDPA (High Speed Downlink Packet Access) which performs a high-speed data communication is standardized.
FIGS. 29A and 29B show an arrangement of a general error control apparatus using the HARQ. This arrangement is not provided with an interleaving and a rate matching functions. FIG. 29A shows an arrangement of a transmitting side error control apparatus 100x. 
The error control apparatus 100x is composed of an error detecting encoder 110, an error correcting encoder 120 and a modulator 190. It is to be noted that for the error detecting encoder 110 and the error correcting encoder 120, e.g. a CRC adder 110 and a turbo encoder 120 may be used.
FIGS. 30J-30L show data examples in the transmitting side error control apparatus 100x. The operation example of the transmitting side error control apparatus 100x shown in FIG. 29A will now be described referring to FIGS. 30J-30L.
The error detecting encoder 110 outputs transmission data 60 (see FIG. 30J) to which an error detection encoding is performed, e.g. error detecting encoded data 61 (see FIG. 30K) to which an error detecting CRC code is added. The error correcting encoder 120 performs turbo-encoding to the data 61 to obtain e.g. error correcting encoded data 62 (see FIG. 30L). The modulator 190 transmits the data 62, e.g. modulated data 63 to which a spreading modulation processing is performed, to a wireless line (in FIG. 30L) or a wired line.
FIG. 29B shows an arrangement of a receiving side error control apparatus 200x. This error control apparatus 200x is provided with a demodulator 230x, a combiner (merging portion) 270x, an error correcting decoder 320x and a code error detector (CRC detector) 330x connected in series.
Also, the error control apparatus 200x is further provided with a buffer 350x connected to the combiner 270x and a buffer controller 340x connected to the buffer 350x and the code error detector 330x. 
FIGS. 30T-30X show data examples in the receiving side error control apparatus 200x. The operation of the error control apparatus 200x will now be described referring to FIGS. 30T-30X.
In the error control apparatus 200x, the demodulator 230×demodulates the received modulated data 63 into demodulated data 70 (see FIG. 30T) quantized. The demodulated data 70 are provided to the combiner 270x. 
The combiner 270x provides, to the error correcting decoder 320x, soft decision information 72 in which data preliminarily stored in the buffer 350x (see FIG. 30U; if the number of quantized bits is supposed to be e.g. 5 bits, a required memory capacity of the buffer is M0=15060 bits) and the demodulated data 70 (see FIG. 30V) are combined or merged.
It is to be noted that FIGS. 30U and 30V show the data examples in a case where a S/P converter (not shown) is inserted between the demodulator 230x and the combiner 270x of FIG. 29A and a P/S converter (not shown) is inserted between the combiner 270x and the error correcting decoder 320x. 
In these data examples, the demodulated data 70 (see FIG. 30T) are series-parallel-converted into systematic bit series data 71_1, first parity bit series data 71_2 and second parity bit series data 71_3 (see FIG. 30U; hereinafter, occasionally referred to as systematic bit 71_1, first parity bit 71_2 and second parity bit 71_3) by the S/P converter (not shown). Then, the data are parallel-series-converted into soft decision information 72 by the P/S converter (not shown) after processing at the combiner 270x. 
The error correcting decoder 320x performs decoding for correcting a code error of the soft decision information 72 to output soft output data 73 (see FIG. 30W) and hard decision result data 74 (see FIG. 30X).
When the code error detector 330x detects a code error of the hard decision result data 74 in which the code error should have been corrected and that the data have an error, the code error detector 330x transmits a data retransmission request 75 to the transmitting side error control apparatus 100x, requests the transmitting side error control apparatus 100x to retransmit the data, and provides the buffer controller 340x with a “NG” decision signal 50x indicating that the data have a code error.
Also, in the absence of an error, the code error detector 330x provides the buffer controller 340x with an “OK” decision signal 50x indicating that the data have no error. When the decision signal 50x is “OK”, the buffer controller 340x clears the buffer 350x and when the decision signal 50x is “NG”, the buffer controller 340x holds the buffer 350x. 
FIG. 31 shows an arrangement of a transmitting side error control apparatus 100y performing a HARQ encoding processing in the 3GPP. This error control apparatus 100y is different from the error control apparatus 100x shown in FIG. 29A in that a bit separator 130, a first rate matching portion 140, a virtual IR buffer 150, a second rate matching portion 160 and an HS-DSCH interleaver 180, which are all connected in series, are provided between the error correcting encoder 120 and the modulator 190.
The first rate matching portion 140 is composed of an RM_P1_1 portion 141 and an RM_P2_1 portion 142 respectively performing a rate matching of a first parity bit 83_2 and a second parity bit 83_3.
The second rate matching portion 160 is composed of an RM_S portion 161, an RM_P1_2 portion 162 and an RM_P2_2 portion 163 respectively performing the rate matching of a systematic bit 84_1, a first parity bit 84_2 and a second parity bit 84_3.
FIGS. 32J-32P show data examples in the transmitting side error control apparatus 100y. The data examples are ones of the HARQ encoding processing in the 3GPP, and a turbo code is used as an error correcting code.
The operation of the error control apparatus 100y will now be described referring to the data examples.
The CRC adder (error detecting encoder) 110 performs CRC addition processing, and outputs error detecting encoded data 81 (see FIG. 32K) which are transmission data 80 (see FIG. 32J) to which the error detecting CRC code is added. The turbo encoder 120 outputs turbo encoded data 82 (see FIG. 32L) which are the encoded data 81 to which the error correction encoding is performed.
The bit separator 130 separates the error correction encoded data 82 into systematic bit series data 83_1, the first parity bit series data 83_2 and the second parity bit series data 83_3 (see FIG. 32M; hereinafter occasionally referred to as systematic bit, first parity bit and second parity bit respectively).
The first rate matching portion 140 outputs the systematic bit series data 84_1, the first parity bit series data 84_2 and the second parity bit series data 84_3 (see FIG. 32N; hereinafter occasionally referred to as systematic bit, first parity bit and second parity bit respectively) in which the transmission rates of the systematic bit 83_1, the first parity bit 83_2 and the second parity bit 83_3 are adjusted.
The virtual IR buffer 150 temporarily stores the systematic bit 84_1, the first parity bit 84_2 and the second parity bit 84_3.
The bit collector 170 takes predetermined systematic bit series data 85_1, first parity bit series data 85_2 and second parity bit series data 85_3 (see FIG. 320), by second rate matching, out of the systematic bit 84_1, the first parity bit 84_2 and the second parity bit 84_3 stored in the virtual IR buffer 150, and outputs encoded data 86 (see FIG. 32P) in which bits are collected.
The interleaver 180 outputs data (not shown in FIGS. 32J-32P) which are the encoded data 86 interleaved, so that the modulator 190 outputs data which are the output data of the interleaver 180 modulated.
It is to be noted that the virtual IR buffer 150 is for holding data to be retransmitted, and the memory capacity thereof is variable according to the performance on the receiving side. In this example, a value (2008 bits) corresponding to the half of the encoding ratio is used.
FIG. 33 shows an arrangement of a prior art error control apparatus 200y on a receiving side. The error control apparatus 200y receives data 88 transmitted by the transmitting side error control apparatus 100y shown in FIG. 31.
The error control apparatus 200y is different from the error control apparatus 200x shown in FIG. 29B in that de-spreaders 210y_1-210y_n (hereinafter, occasionally represented by a reference numeral 210y) connected in parallel and a rake combiner 220y connected to the de-spreaders 210y are connected to the previous stage of a demodulator 230y, a deinterleaver 240y, a bit separator 250y and a second rate matching portion 260y connected in series are inserted between the demodulator 230y and a combiner 270y, and a first rate matching portion 280y and a bit collector 290y connected in series are inserted between the combiner 270y and an error connecting decoder 320y. 
The second rate matching portion 260y are composed of an RM_S portion 261, an RM_P1_2 portion 262 and an RM_P2_2 portion 263 performing a rate matching of a systematic bit 91_1, a first parity bit 91_2 and a second parity bit 91_3 respectively.
The first rate matching portion 280y are composed of an RM_P1_1 portion 281 and an RM_P2_1 portion 282 performing a rate matching of a first parity bit 92_2 and a second parity bit 92_3 respectively.
FIGS. 34T-34Z show data examples in the receiving side error control apparatus 200y. The data examples are ones prescribed by the 3GPP, and the turbo code is used as an error correcting code.
The operation of the error control apparatus 200y will now be described referring to the data examples in FIGS. 34T-34Z.
In the error control apparatus 200y, a de-spreading processing, rake combining processing, a demodulation processing and a deinterleave processing are respectively performed to the received data by the de-spreader 210y, the rake combiner 220y, the demodulator 230y and the deinterleaver 240y, so that the data are converted into quantized data 90 (see FIG. 34T) to be provided to the bit separator 250y. 
The bit separator 250y separates (series/parallel converts) the data 90 into the systematic bit series data 91_1, the first parity bit series data 91_2 and the second parity bit series data 91_3 (see FIG. 34U; hereinafter, occasionally referred to as systematic bit 91_1, first parity bit 91_2 and second parity bit 91_3).
The second rate matching portion 260y provides, to the combiner 270y, systematic bit series data 92_1, the first parity bit series data 92_2 and the second parity bit series data 92_3 (see FIG. 34V; hereinafter, respectively referred to as systematic bit 92_1, first parity bit 92_2 and second parity bit 92_3, and occasionally represented by soft decision information 92) in which the rate matching is performed to the systematic bit 91_1, the first parity bit 91_2 and the second parity bit 91_3, respectively.
When the data are not retransmitted data, namely, when the buffer 350y is cleared at the time of the initial data transmission or by the buffer controller 340y, the combiner 270y provides the data 92_1-92_3 as they are to the first matching portion 280y, and provides the data 92_1-92_3 (see FIG. 34V; if e.g. quantized bit number is supposed to be 5 bits, the required memory capacity of the buffer 350y is M1=10040 bits) to the buffer 350y. 
The first rate matching portion 280y provides, to the bit collector 290y, systematic bit series data 93_1, first parity bit series data 93_2 and second parity bit series data 93_3 (see FIG. 34W; hereinafter occasionally referred to as systematic bit 93_1, first parity bit 93_2 and second parity bit 93_3, respectively) in which the rate matching is performed to the combined data 92_1-92_3.
The bit collector 290y provides, to the error correcting decoder 320y, soft decision information 94 (see FIG. 34X) in which the bits of the data 93_1-93_3 are collected to be arranged. The error correcting decoder 320y performs turbo decoding processing (error correction processing) to the encoded data 94, outputs soft output data 95 (see FIG. 34Y; not shown in FIG. 33), and performs hard decision processing to output hard decision result data 96 (see FIG. 34Z).
It is to be noted that the hard decision result data 96 are data resulting from error correction decoding, and the soft output data 95 are data composed of the hard decision result data 96 and reliability information of the hard decision result data 96.
The CRC detector 330y detects an error of the hard decision result data 96, and provides, to the buffer controller 340y, a decision signal 50y which is a decision result as to whether an error is present or absent. Also, when detecting the error of the hard decision result data 96, the CRC detector 330y requests the transmitting side error control apparatus 100y to retransmit the data. It is to be noted that FIG. 33 does not show a functional portion performing a retransmission request.
The buffer controller 340y clears the buffer 350y when the decision signal 50y indicates “OK”, and holds the data of the combiner 270y when it indicates “NG”.
Also, when the data 92_1-92_3 are retransmitted data, namely when the data are held in the buffer 350y, the combiner 270y outputs combined data 92_1-92_3 in which the data 92_1-92_3 and the data 92_1-92_3 held in the buffer 350y are combined. The combined data 92_1-92_3 are held in the buffer 350y. 
As an error control method and device for reducing a retransmission data amount (the number of packets), there is “error control method and communication system using the method” conventionally known (see e.g. patent document 1).
In this error control method, a transmitter (transmitting side error control device) divides codewords obtained by performing error correction encoding to information into a plurality of packets to be transmitted. A receiver (receiving side error control device) measures reliability of each packet received, requests the transmitter to retransmit the packet when a predetermined condition based on the reliability is satisfied, combines a plurality of packets received including the retransmission packets, and decodes codewords thus obtained.
Namely, the receiving side error control device does not request to retransmit the entire codewords but requests to retransmit only a packet whose reliability is low within a plurality of packets composing the codewords. Thus, the amount of the data retransmitted is reduced.
(Patent document 1)
Japanese Patent Application Laid-open No. 2001-119426
However, since the error control apparatuses 200x and 200y shown in FIG. 29B and FIG. 33 hold soft decision information before the error correction decoding in the buffer 350y, the buffer 350y requires a capacity of “error correction code length”×“the number of quantized bits of soft decision information”.
Namely, supposing that a transmission data length is “Ld”, the encoding ratio of error correction encoding is “1/3 ”, the number of quantized bits of the soft decision bits is “Nr” bits, a buffer of about 3×Ld×Nr bits is required, which makes the buffer memory amount large.
For example, the required memory capacity M0 of the buffer 350x shown in FIG. 29B is 5×1004×3=15060 (bits) as shown in FIG. 30U. Also, the required memory capacity M1 of the buffer 350y shown in FIG. 33 is 5×(1004+502+502)=10040 (bits) as shown in FIG. 34V.
Also, in the above-mentioned error control method for reducing the retransmission data amount, when a method by which the retransmitted data and the soft decision information before the error correction decoding are combined is adopted, the buffer memory capacity required assumes the same as that of the error control apparatus shown in FIGS. 29B and 33.